Chip design’s recycle cycle: Interview with Aart de Geus, chairman and co chief executive, Synopsys

The looming problem then was convincing in house design teams to build blocks that could be reused. "Economically, the incentive for reuse is a global one; the incentive for success is a local one," he claimed. Looking back during an interview at this summer's Design Automation Conference, de Geus explained: "During the past decade, IP came to mean commercial IP – ARM is the perfect example. Synopsys is the second best example: the second largest supplier of commercial IP, with a portfolio that is broader than and complementary to ARM's." De Geus adds: "I think we are still in the early phases of this shift. Not only is there more IP coming, there is more complex IP coming and more reuse coming." And the IP is coming in different formats, including platform based design – in which a number of IP cores are preassembled into a skeleton design to keep design costs under control. With a platform based design, teams choose to couple design IP with verification IP to test the blocks in the context of a complete SoC. "There is so much interest in verification IP now," says de Geus. De Geus believes the concept of the platform itself is nothing new. "Take Texas Instruments' OMAP: that started in the 1990s. The idea of reusing IP is orthogonal to the topic of platforms, but when you bring the two together, you have something interesting; rapid technical evolution, while retaining a high degree of flexibility so you can adapt to market needs." Yet complexity brings its own problems. "I had full control over and full understanding of the blocks I used yesterday," de Geus notes. "I understand what the blocks I have today are supposed to do, but I'm not entirely clear how they do it." Using the example of recently launched protocols such USB3, de Geus claims: "The specification of these things is telephone book size." Yet, he says, if a company builds a USB3 core, 'there is no differentiation to be had'. "The block needs to work within the context of a complete SoC – but that is it. If you're an ic supplier or system house, what will be your differentiation? If you want to build a castle, the differentiation is not in the Lego blocks you use, it's in the castle you want to build." The complexity of the blocks used to assemble an IC has changed dramatically over the years. The era of schematic capture gave designers their first taste of IP. De Geus explains: "The NAND gate was an incredible IP block when it became one; now, it feels 17th Century. Then came adders and multipliers, followed by the microprocessor. Somewhere during that process, the design became a hardware and software beast. Today, the blocks within an SoC are configurations of hardware and software. "The way to make a platform do something different is to put different software on top. That doesn't tell you anything new architecturally, but in the context of chip design it is new. You have a zillion little computers in this box; you have many compute cores and the cores are heterogeneous and may look very different from the traditional von Neumann machine," says de Geus. "The silicon provides the physical reality, but the software is the functional reality of that platform. When we talk about SoC assembly, we need to talk about the software and hardware assembly and to make sure the two stay in sync. That is why Synopsys has invested so heavily in hardware-software prototyping – we are seeing so many customers heading there." One issue for an EDA tools supplier in the era of these giant multiprocessor SoCs is the number of companies with the resources to design them. The direction appears to be one of consolidation in SoC design. De Geus argues: "For Synopsys, it has not been an issue. The most successful companies continue to do more complex designs, but that means they do more business with us and are looking for a much closer relationship." The tools themselves and the relationships between them are more complex, which requires close cooperation between design team and tools supplier, de Geus says. "The designer is the guy driving the race car trying to win the grand prix. We are the pit crew. When the pit crew says you need to change your tyres, you do it, or you won't win. It's a team game." Although the EDA companies continue to add tools to their portfolios that address technologies such as formal and system level design, de Geus sees a continuing evolution of the current platform based methods. "The design verification field is going through the next wave of change. And the notion of verification IP is central to that. "Formal technology applies to places where there is a very strict description. When you say 'let me assemble something from Lego pieces', there is no formal top level," says de Geus. Similarly work continues on system level design techniques, but as adjuncts to existing methods. "There will be more effort. But when people say 'start with C and synthesise it', this is beyond dreaming. It is mentioned by people who have no idea of what chip design really is about." Aart de Geus Aart de Geus, chairman and co chief executive of Synopsys, has a Masters degree in Electrical Engineering from the Swiss Federal Institute of Technology and a PhD from Southern Methodist University. Previously, he managed the advanced computer aided engineering group at General Electric's North Carolina facility. When GE exited the semiconductor business in 1986, de Geus and partners set up a company called Optimal Solutions. When the company moved to Silicon Valley, it was renamed Synopsys – a hybrid of synthesis and optimisation. Amongst his industry honours are the IEEE Robert N Noyce Medal in 2007, the Spirit of the Valley Lifetime Achievement Award, also in 2007, and the Global Semiconductor Alliance's Morris Chang Exemplary Leadership Award in 2009.