Engineering publications brought to you by Mark Allen

EDA & Design Software

Upgrade allows SoC designers to optimise for speed, area and power

Thermal management package integrates mechanical and electronic design domains

Cadence looks to knock Synopys off its IP perch

Tanner backs OpenAccess to improve analogue and mixed signal design

Building an IP-XACT design and verification environment with DesignWare IP

Cadence to acquire analogue IP start up

Renesas applies software test and verification to automotive SoCs

Forget design for reuse; the new mantra is ‘build for change’

ARM, Altera collaborate on SoC design tools

Outlook 2013: Accelerating innovation and time to market

Chip design’s recycle cycle: Interview with Aart de Geus, chairman and co chief executive, Synopsys

How real number modelling is easing the analogue simulation challenge