The Vivado Lab Edition is a lightweight programming and debug edition of the Vivado Design Suite. It includes the Vivado Device Programmer, Vivado Logic and Serial I/O Analyzer, as well as memory debug tools.
The Vivado Lab Edition is 75% smaller than the complete Vivado Design Edition, reducing set up time and system memory requirements. For design teams that require remote debug or programming over Ethernet, the Vivado Design Suite 2015.1 also provides a standalone hardware server, which is less than 1 percent of the complete Vivado Design Edition.
Vivado Design Suite 2015.1 also features advancements in the simulation flows that speed LogiCORE IP compile times. As a result, overall simulation performance is said to be 20% faster than previous releases. The release also includes simulation flows integrated with those of Aldec, Cadence, Mentor Graphics and Synopsys.
Xilinx has also included interactive clock domain crossing (CDC) analysis capability. This is said to boost productivity by enabling the debug of CDC issues earlier in the design and to speed time to market.
Meanwhile, speeding the development of Zynq-7000 based products, the Xilinx SDK now allows developers to analyse the performance and bandwidth of their SoC design, with a number of key performance metrics available.
