But there is a price to pay; literally and figuratively. Making sure those designs work as their creators envisaged is becoming even more complex and time consuming. In fact, is suggested that a 22nm chip design will cost $90million and that verification of the design could represent 60% of that figure.
Where once verification was a task addressed at the latter stages of the development cycle, today's chip designers want to verify their creations as early as possible. The concept is being termed 'shift left'; a reference to the time axis if the design cycle was represented on a chart. The reason? It's not just the various blocks in an SoC that need to be verified, it's also how those blocks interact. And finding out late in the design cycle that a product isn't working as intended can mean the company has to take a major financial blow.
Alain Bismuth, chief marketing officer for Tabula, noted: "Any attempt to reduce design cost or development time has to address verification. But the problem with verification is that functional coverage is limited; you can't achieve the same coverage of corner cases as you could in a real deployment."
Looking to address these challenges, Tabula has developed what it calls DesignInsight. The technology enables users of its ABAX2 programmable logic devices to have what the company calls 'unprecedented real time observability' into the inner workings of their design, coupled with a verification methodology that spans from RTL simulation to systems deployed in the field.
When Tabula was founded, it wanted to improve the overall experience of working with complex chips. Its starting point was the Spacetime architecture, a way it believes makes FPGAs more attractive economically.
When Spacetime was launched, Bismuth claimed: "Time is the third dimension. Tabula emulates the third dimension by reconfiguring the device up to eight times per cycle. Our software will look at the RTL and determine which portion is performed at what point and will generate configuration code automatically that allows the device to perform the given tasks."
Steve Teig, Tabula's founder and chief technology officer, noted the company realised that users of its devices not only needed Spacetime, they also needed observability – some way of looking inside the chip while it's running.
"Observability has many facets – functional behaviour, for example," he said. "You want to find things that surprise you. Observability is like verification, but it also allows you to look at performance."
In a white paper explaining DirectInsight, Tabula says 'Better observability and reuse of the simulation methodology in post silicon validation phases would reduce time and expense of silicon device development significantly. Tabula has developed such a methodology'.
DesignInsight technology comprises three elements:
•
Architecture: The Spacetime 3D programmable architecture, with a state element based interconnect and fine grained reconfigurability.
•
Silicon: The 22nm ABAX2P1 device, with an integral 2GHz configuration network, configurable trace buffer, on the fly signal reconstruction unit and programmable trigger unit, and
•
Software: Stylus software enables the automated reconstruction of signals optimised away in synthesis.
In this way, DesignInsight enables users of the ABAX2 device to have what Tabula calls 'unprecedented real time observability into the inner workings of their design', as well as a verification methodology that spans from RTL simulation to systems deployed in the field (see fig 2).
Signals in a production design operating at up to 2GHz can be seen without the need for recompilation or predeclaration of target signals. According to the company, this will reduce development costs, accelerate the time to market and increase system reliability.
"Even when the chip is running at 2GHz," Teig noted, "DesignInsight doesn't use any resources. It may sound impossible, but that is what we're talking about. It is achieved by having a little bit of stuff on every chip, but also through a software environment that users can interact with; it's part of the fabric."
Bismuth said one approach used generally before silicon arrives is assertions. "These statements of design intent are developed in parallel with RTL. Separate assertions can be written that enable verification."
Once silicon has come back from the fab, its performance becomes less observable. "There is better functional coverage because the chip can be put into a real deployment, but this comes at the price of less observability. Meanwhile," he continued, "changes are hard to make and costly. And when the device is deployed in the field, observability becomes very poor."
A potential solution is to include an instrument on chip; building in some form of logic analysis. "However, as you build the chip, you have to predict where the problems may be. You also modify the design and that could create further problems, whilst masking problems in the original design."
Andrea Olgiati, director of DesignInsight at Tabula, said: "With DesignInsight, you can look at any RTL signal when the design is running at up to 2GHz. Unlike SystemVerilog assertions, you can see the signal without recompiling at any point."
According to Olgiati, this is enabled by a number of pieces of Tabula technology. "Architecture, chip design and compiler," he noted. "All these contain the things that make DesignInsight possible."
Designers can specify a list of signals to be observed and the conditions for triggering and storing those signals. This specification is compiled into an independent verification module called a view. Each view takes the general form of 'when a==b, trace c,d,e'.
Each ABAX2 device contains trigger and trace units (see fig 1). The trigger unit evaluates 'when a==b'. When this statement is true, it sends a signal to the trace unit. "This concerns itself with the 'trace c,d,e' clause," said Oligiati. "When it receives a signal from the trigger unit, it starts capturing the data requested by the user."
There is also a reconstruction unit. "Due to ABAX2's high performance, the Stylus compiler must optimise aggressively the netlist created from the user design to meet timing,"
Olgiati continued. "This can result in a netlist that doesn't have all the necessary components readily available on the fabric. The reconstruction unit takes the available information and reconstructs user signals before they are evaluated for triggering/tracing.
"For instance, assume the user has defined 'a=f+g' and that a is not available – it may have been optimised away. If f and g are available, the reconstruction unit will perform an addition and present a to the trigger unit for evaluation."
"There is no limit to the number of views," Teig noted. "We believe this model unifies verification, allowing the same assertions you had before silicon to be carried through the lifetime of the design. And, as you learn more about the design, you can add new assertions. It's the first technology to offer observation without compromise," he concluded.
