Embedded System Access: changing the paradigm of electrical test

Test strategies are graded by how close they come to the ideal test solution; something which doesn't add any cost to the product under test during design and production. Most agree that product testing is necessary as part of design validation, as a quality indicator for manufacturing process control and for the detection of defective products prior to shipping. However, test solutions must meet certain requirements: test development and execution should be fully automated and should be quick; test equipment should be inexpensive; and there should be 100% fault coverage. But the cost of test is now a significant part of the overall development and manufacturing cost. The reason is the complexity of today's high speed designs and the lack of available test access for many printed circuit board assemblies, or boards. While boards look more like integrated circuits due to the loss of access to internal circuit nodes, the rapid development of 3d ICs with multidie integration brings structures that are similar to boards and systems. The 3d board with little physical access is on the horizon. At the same time, the combination of new packaging and integration technologies has brought further complexity. While multiple boards were needed several years ago to create complete system designs, today, some of these systems can be realised as SoCs or System In Package (SIP) designs. As a result, board size can be minimised and super complex systems can be created. No matter how a design is arranged, the fundamental question from the test engineering perspective is how these complex systems can be tested appropriately and efficiently. Non invasive test access 'Divide and conquer' is a strategy suited to the test arena. Partitioning circuit structures into testable elements is a prerequisite for a successful test strategy. This is one of the reasons why in circuit test (ICT) became so successful at the board level. ICT approached circuit test structurally, testing components individually. But the bed of nail based invasive test access is becoming a problem with modern boards. Test access problems were predictable, which resulted in the creation of IEEE1149.1 in 1990. Developed by the Joint Test Action Group (JTAG), this standard moves the pin electronics of a tester into the unit under test (UUT) in order to enable non invasive test access without bed of nail adaptors. But the test bus needs to be incorporated into the UUT by the board designer, with test access provided implicitly, rather than as an afterthought. The success of IEEE1149.1 is down to the open expandability of its register architecture, combined with the universal test bus interface (Test Access Port, TAP) and its protocol definition. These properties allowed IEEE1149.1 to become the base technology for new non intrusive methodologies and standards for testing, debugging, programming and emulation. As a result, the portfolio of test access strategies at the board level has changed. Today, there are three principal access strategies: • Native Connector Access (access through design integrated I/O interfaces) • Intrusive Board Access (access through physical test nails and probes) • Embedded System Access (access through design integrated test bus) While these are not mutually exclusive, the combination of these strategies depends on the chosen automated test equipment (ATE) platform. A look at the qualitative development of trends for the various access strategies reveals interesting facts, including a long adoption period of IEEE 1149.1 as the first representative for ESA. In 2008, sales of boundary scan products reached around $29million, while sales of intrusive ATE were around $500m. Today, we see a rapid transition from intrusive access strategies to ESA. The adoption of ESA is primarily due to the fact that it is now a class by itself, comprising such non invasive access technologies as: • Boundary Scan Test (IEEE1149.1/.4/.6/.7) • Processor Emulation Test (PET) • Chip Embedded Instrumentation (IJTAG, IEEE P1687) • In System Programming (ISP) • Core Assisted Programming (CAP) • FPGA Assisted Test (FAT) • FPGA Assisted Programming (FAP) • System JTAG (SJTAG) In addition, there are a number of other technologies and standards, such as On-Chip Emulation (OCE) for software validation. The electrical access embedded in the target system allows ESA to work without invasive test nails and probes. In principle, every ESA technology uses a task specific pin-electronic which is controlled by the test bus. As a result, it can execute test functions and programming routines directly in the target system. This target system can be a chip, a board or a complete system. A detailed analysis of key ESA technologies at the board level reveals differences in operation and goals. Table 1 shows the complementary character of the various technologies. Boundary scan uses boundary scan cells, combined into a boundary scan register, as primary access points for a target system's circuit nodes. The boundary scan register is accessed and controlled through the TAP and all vectors are scanned serially. The test bus comprises four mandatory signals and a fifth optional reset signal. Boundary scan is a structural methodology and provides excellent fault diagnostics, especially for connectivity tests on bga packaged devices. However, since boundary scan tests are static in nature, dynamic defects usually cannot be detected, let alone be diagnosed. In addition to IEEE1149.1, various related standards have been created or are in development. Processor Emulation Test (PET) uses the debug interface (implemented for software validation in many microprocessors) to transform the processor core temporarily into a native test controller. The processor and its system bus interface become the pin electronics used as access points for the connected circuitry in the target systems. Controlled through the boundary scan interface or some other debug interface, the processor core uses write and read access to the system bus with respective test vectors to manipulate and test the connected internal and external resources and components. No operating system or flash firmware is necessary and PET can detect static and dynamic defects. However, diagnostics are limited due to the functional test approach. PET complements boundary scan and enables or improves the test of dynamic components such as DDR-SDRAM, gigabit interfaces and other components that cannot be scanned at chip, board, and system level. One of the various PET solutions available the VarioTAP technology. Chip embedded instruments are intellectual property (IP) blocks integrated into ICs and often accessible through the boundary scan port. The functionality of chip embedded instruments is open and ranges from simple sensors to complete analysis instruments and programming engines. The IP is either integrated permanently in the chip (hard macro), or it can be instantiated temporarily and configured (soft macro) in fpgas. As a result, the pin electronics are unrestricted in principle and can provide a variety of functionality, subject to the host device. Such chip embedded instruments can be active during normal system operation, which enables interesting test and debug applications. FPGA embedded instruments have enjoyed strong interest recently. By enabling strategies such as FPGA Assisted Test (FAT) and FPGA Assisted Programming (FAP) they provide the flexibility needed for individual test and measurement requirements. Chip embedded instruments have been used for years in chip test: for example, built in self test (BIST) IP. However, access to these instruments has not been standardised, something that will chang with IEEE P1687 (also known as IJTAG). One of the leading system technologies for the holistic support of chip embedded instruments is ChipVORX. Device programming also benefits from ESA technologies. By using the same infrastructure as the test solutions discussed aboce, a high degree of synergy between test and programming applications can be obtained. In System Programming (ISP) is a collective term for the programming of flash devices via Boundary Scan and for the programming of pld/fpga devices through their TAP and built in programming registers, while the devices are mounted on the pcb. Special standards exist for in system programming of plds and fpgas, including IEEE1532, JESD-71 and an industrial standard called Serial Vector Format (SVF). The premise of the Core Assisted Programming (CAP) strategy is similar to Processor Emulation Test. The processor is controlled through its native debug interface in a way that allows flash or fpga (design permitting) connected to the system bus to be erased, programmed and verified. In the case of flash, it does not matter whether it is integrated in the mcu, for example, or connected as an external device. Furthermore, it is possible to load only the flash handler/programming engine via boundary scan into the processor and to download the flash data image through a high speed communication interface on the processor. CAP technology, such as VarioTAP, provides higher in system programming speed than boundary scan based device programming. One of the most interesting technologies for flash ISP, referred to as FPGA Assisted Programming (FAP), is based on fpga embedded instruments. The embedded instrument in this case is a programming engine (programmer) soft macro, typically provided by a tool vendor and downloaded temporarily into the fpga. Depending on the architecture of the programmer IP and the performance of the external control system, drastic improvements in programming speed are possible compared to boundary scan based ISP. Meanwhile, universal, synthesis free solutions exist for FAP, such as those provided by ChipVORX. The last access technology in this discussion is System Level JTAG. While remote control through an external controller is possible, this technique typically employs a central test control unit integrated directly into the system design. Test vectors are usually stored locally on the system and a separate IC is commonly used as the test bus controller, although there is the possibility to integrate the test bus controller function in another IC. This method can be employed not only for individual boards, but also for systems with multiple boards and modules. The transformation to the system-integrated tester The transition from traditional invasive test access and techniques to ESA is a fundamental technological metamorphosis. These changes include: • integration of test electronics in the system under test, • inseparable coupling of functional and test circuitry in the system design • forming of partitioned test centres with various features, • wider range of test and programming strategies; • possible use throughout the entire product life cycle, • flexibility of reconfigurable pin electronics with fpgas, • availability of new instrumentation platforms. In practice, ESA represents a transformation from a purely functional design into a functional design with integrated test capabilities – a combination of unit under test and tester. Depending on the implementation of ESA, a variety of applications is possible. Currently, fpga based test is a technology driver for progressively more complex test and measurement functions. This includes applications such as: • voltage measurement • frequency measurement • temperature measurement • bit error rate tests for high speed signals • event counters, and • logic scopes. As a result, extensive design validation is possible in the lab or even at the designer's desk through one central communications and control channel. One advantage of this methodology is that signals are accessible and measurements are taken directly inside the circuitry, avoiding artificial interference and distortion caused by mechanical probes, cables and additional electrical loads. With ESA, test and measurement results are not only more accurate, but also more reproducible. Of course, for an efficient application of ESA techniques respective external instrumentation is needed. While we have mainly talked about the boundary scan interface as the test bus, there are a number of proprietary bus interfaces, inclufing Serial Wire Debug (SWD), Spy-Bi-Wire (SBW) and or Background Debug Mode (BDM). For ATE vendors, this means their test bus controllers need to provide the flexibility to support any of such interfaces; even a mix of different test bus interfaces in multiprocessor applications should be supported. The various ESA technologies must also be supported by powerful software tools and must be made available through intuitive graphical user interfaces. In this context, we need to consider not only the independent use of individual ESA methods, but also the interactive application of various ESA technologies in order to gain extra benefits. This last requirement leads to another important topic: the combination of ESA with other access technologies, such as Invasive Board Access (IBA) and Native Connector Access (NCA), allowing ESA to be migrated into existing test systems. To support this level of interactivity, ESA test equipment needs to provide very good integration features and must be available for all important integration platforms. Functional test, in particular, will play an important role, considering the continued rise of very powerful and open test and measurement platforms such as PXI. The transition to ESA with all its facets requires a new class of JTAG/boundary scan instrumentation, putting pressure on ATE vendors. First solutions are available in form of multidimensional JTAG/boundary scan platforms The term 'multi dimensional' reflects the support of the various dimensions and complexities of parameters, structures, functions, interactions, applications and access technologies that come with ESA. One of the first such platforms is based on SCANFLEX hardware and SYSTEM CASCON software. Summary and outlook The trend towards non invasive test access strategies has spawned a number of new technologies and methodologies which have, in turn, resulted in ESA techniques. The essence of ESA is the provision of test pin electronics in the target system itself. Activating ESA results in a temporary transformation of the system, allowing it to be tested in partitions by embedded test centres under control of the integrated test bus. Key elements of this infrastructure include boundary scan devices, microprocessors, fpgas and devices such as asics with chip embedded instruments. The transition to ESA enables the observation and stimulation of signals directly in the circuitry, without signal distortion, making it a perfect foundation for the test of high speed signals. At the same time, ESA provides enormous potential for new test and measurement applications. Further ESA developments will be influenced by new standards related to the test bus interface, such as IEEE1149.7, by the control of chip embedded instruments as defined in IEEE P1687 and through features defined in the latest revision of IEEE 1149.1. In addition, new instrument IP - either hard macros or fpga embedded soft macros - will drive the innovation in test, measurement and programming applications and will continue to blur the lines between chip test and board test. While we don't expect the industry as a whole to suddenly change direction to ESA as the strategy of choice within the next few years; migration strategies and combinations of access techniques will be the key, since invasive test access will remain widely used during this decade. Author profiles: Thomas Wenzel is managing director of GOEPEL electronic's JTAG/Boundary Scan division. Heiko Ehrenberg is president of GOEPEL electronics LLC.