FPGA developers square off at 20nm

Until recently, the two market leaders – Altera and Xilinx – tended to compete on the basis of what customers could use. But lately the focus has moved to what customers might be able to use at some unspecified time in the future. And their battle is now centred on 20nm technology. Altera made the first move in the campaign at the beginning of October 2012, outlining what its customers might see at 20nm. A number of claims were made by Brad Howe, senior vp for R&D. Amongst them were a 60% reduction in power consumption, greater transistor density and even higher speed transceivers. The devices will start to appear in 2014, Howe claimed. "Our innovations at 20nm will allow us to deliver a highly efficient, highly flexible mixed system fabric that features optimal levels of dedicated circuitry with the latest 20nm fpga process technology," said Howe. "The result is a device that delivers the industry's highest levels of integration, performance and bandwidth at the lowest power." Now, it's Xilinx' turn. Claiming it was first to ship 28nm devices, the company says it is keen to maintain what it calls a 'generation lead'. Giles Peckham, European marketing director, said: "[The 20nm strategy is] building on what Xilinx can offer at 28nm, where we announced a breakout strategy that moved programmable logic on towards all programmable logic, including SoCs and 3d ics." Central to Xilinx' 20nm plans is offering developers 'more bang for their buck'. In Peckham's opinion, 20nm devices will not only offer the best power/performance, they will also allow engineers to take a system level view of their designs and to get products to market more quickly. Whereas the focus in the past has been almost entirely on the silicon, far more attention is now being paid to the design tools. The subtext here suggests that if you don't have design tools that are up to the job, there's no way that you will be able to take advantage of 20nm technology. "Designers need tools," Peckham asserted. And Xilinx' offering is Vivado, something which it believes will cut the design effort from months to weeks. "Already, all customers for the V2000T have used Vivado, as have 80% of high end designs," Peckham continued. "At the 20nm node, Vivado will be the foundation for design and the way to get the best out of the technology." One of the benefits claimed for Vivado is that it introduces an IP centric approach to high level design. "People looking to use 20nm technology will need to move to higher levels of abstraction," Peckham counselled. Vivado will also be capable of taking C/C++/SystemC code and converting it to hardware. Vivado will also help designers deal with bugs. A common database approach supports cross processing, allowing designers to look back in time to see where issues originated. "It will be easier to solve problems at the rtl level, rather than at place and route," Peckham observed. Giving an indication of the productivity improvements likely to be available from Vivado, Peckham used the example of a large design locked down, with no late changes and with reuse of design elements from a previous product. "Using older tools, two to three months to design is a reasonable estimate. Vivado will cut that to two to three weeks." But it's the silicon that will do the work and, according to Peckham, the 20nm offerings will bring 'additional dimensions' compared to current devices. "Alongside programmable digital, there will be programmable analogue," he said, "and 3d ics will move to a multichip programming solution. All of this is intended to improve performance and power consumption at the system level, as well as to improve the Bill of Materials." The 20nm node will see all devices made using one base process. "We developed one technology at 28nm in association with TSMC," said Peckham, "allowing us to hit a 'sweet spot'. While the HPLP process didn't offer the highest performance or the lowest power, we can tweak it to create a range of products." Xilinx says it will use this process as a means of driving towards a higher level of system integration, but it is also developing a new metric – power/performance per Watt – to help customers understand the capability of new devices. "We are committed to a 30 to 50% increase in price/performance per Watt at each new node," Peckham pointed out. There will be three broad classes of device at 20nm: fpgas; SoCs; and 3d ics. Alongside more performance, fpgas – which will continue to be monolithic – will have enhanced analogue and mixed signal capabilities. "Customers are looking for the ability to do 12bit conversions at 1Msample/s," Peckham said. "They also have higher expectations about IP, so we will be moving to the block subsystem level to help them complete larger designs." In general, he said fpga technology was being driven by communications applications. "Designers want multiple 100G channels," he said, "and we have to deliver them within the same power budget. With wireless designs, customers are looking to balance power and performance while having access to more dsp functionality." At the 20nm node, fpgas will feature 33G transceivers and the largest device planned will have more than 100 transceivers. System level performance is said to be doubled and, by tuning the architecture, Peckham said utilisation of more than 90% would be possible without routing issues. Meanwhile, at the process level, TSMC has managed to reduce the underlying power consumption, while Xilinx has 'tweaked' the transistors and logic cells, with the result that power consumption will be halved. Second generation SoCs, as the 20nm devices will be called, will move to heterogeneous multicore architectures, with optimised interfaces between the processor subsystem and the fpga fabric. "We will have the opportunity to double the number of logic cells," Peckham said, "unlike monolithic parts, where the shrink will only increase that figure by 50%." Applications driving SoC developments include imaging, video analytics, machine vision and broadcast. Finally, 3d ics will support heterogeneous and homogeneous approaches, offering wider memory interfaces and higher level transceivers; potentially 56G. "Customers for these parts are looking for high performance and peak processing," said Peckham. Interposer technology is critical to the 3d device and Xilinx will be offering two approaches: one supporting heterogeneous dice; the other for homogenous parts. Designs with up to 40m asic equivalent gates may be suited to these parts. As to when 20nm parts might be available, Peckham wasn't giving anything away. "We will be delivering fpgas as soon as TSMC finishes running test chips and so on." But he said Xilinx was already working with lead customers to help them develop next generation products.