As the RISC-V Instruction Set Architecture (ISA) sees increased adoption, there is also growing demand for functional verification of RISC-V-based SoCs. This collaboration provides the RISC-V community with proven flows that can be used to accelerate the verification and software/hardware debug of RISC-V processors and systems.
The first phase of the collaboration supplies reference methodology and scripts for Synopsys VCS functional verification solution and the Synopsys Verdi Debug System with Bluespec. These reference methodologies are Universal Verification Methodology (UVM) compliant, allowing customers to integrate them into their verification flows. In addition, Synopsys and Bluespec are working on additional reference methodologies for static, formal, portable stimulus and FPGA synthesis.
“Creating custom implementations of a RISC-V-based ISA requires significant focus on achieving the highest verification coverage possible,” said Kiran Vittal, senior director of Partner Alliances in the EDA Group at Synopsys. “Collaborating with key ecosystem companies, such as Bluespec, offers customers the ability to jumpstart their RISC-V designs with Synopsys’ optimized EDA flows and methodologies that will help increase verification productivity, performance and throughput.”
"RISC-V is providing an unprecedented number of CPU options, from suppliers to microarchitectures to custom instructions and more," added Charlie Hauck, CEO of Bluespec Inc. "We are happy to be collaborating with Synopsys to provide straightforward design, verification and validation flows to safely and efficiently navigate the RISC-V landscape."
Bluespec offers a broad range of RISC-V-based soft processor IP, a complete RISC-V software development environment running hardware-accurate RISC-V cores in an FPGA-enabled cloud and a turnkey hardware acceleration tool for developing innovative high-performance, low-power RISC-V subsystems.
The company provides three classes of RISC-V processors: the ultra-low resource count microcontroller family (MCU), the bare metal/RTOS family (BMR), which is optimised for performance and resource utilisation, and a Single Core Linux (SCL) family for applications that run on top of Linux.
As part of the collaboration with Synopsys, Bluespec will include reference scripts with the delivery of its processor IP to customers.
The Synopsys Verification Family of products are built from the industry's fastest engines, including Virtualizer virtual prototyping, VC SpyGlass static and VC Formal verification technologies, VCS simulation, ZeBu emulation, HAPS prototyping, Verdi debug and VC Verification IP (VIP).
Newly enhanced native integrations enable performance gains between all verification engines, accelerating time to market for complex RISC-V-based SoC designs.
