The company also announced that it is actively engaged with customers on high performance 2nm ASIC development.
These two announcements put Alchip among the first wave of IC innovators to successfully adopt the revolutionary nanosheet (or, gate all-around, GAA) transistor architecture. The test chip features high-speed SRAM and automatic place-and-route design to ensure optimal performance. It also includes silicon performance monitors for real-time insights and integrates Alchip’s Lite I/O with shared and non-shared power domains, positioning it to handle 3DIC options.
The test chip will establish the design flow and methodology for the latest nanosheet transistor structures. It will also generate power, performance, and area (PPA) data from the 2nm process technology.
According to Alchip, its 2nm test chip tapeout as a critical step in maintaining its high-performance ASIC technology leadership, as the results will help the company prepare for future advancements toward next-generation 1.6nm process technology.
Although it’s a monolithic design, Alchip’s 2nm test chip integrates and validates the company’s AP-Link-3D I/O IP for potential use in future system on 3DIC chiplets designs.
“We’re open for business and ready to serve customer’s 2nm demand. This test chip showcases our ability to push the boundaries of high-performance computing and artificial intelligence design,” said Erez Shaizaf, Alchip CTO.
Johnny Shen, Alchip’s President and CEO, added, “Our 2nm test chip represents a significant leap forward in technology and demonstrates our readiness to engage in the most advanced ASIC development. We’re looking forward to seeing how this breakthrough impacts the semiconductor industry.”
