Alchip unveiled its chiplet technology at the TSMC North America Technology Symposium and is now the first dedicated high-performance ASIC company to announce total design readiness of their design and production ecosystem. The new service targets TSMC’s latest N3E process technology.
The company said that it completed its design technology and infrastructure during the current quarter and will make its design methodology available within a couple of weeks. Other assets in place include a complete library of best-in-class 3rd party IP covering DDR5, GDDR6, HBM2E, HBM3, PCIe5, and 112G SERDES IP from Tier 1 providers.
Alchip has also made available, to select customers, its 3nm MCM, CoWoS and InFO advanced packaging capabilities and its latest APLink 5.0 (Advanced Package Link) die-to-die IP that is UCle 1.0 compatible.
“We have made it a priority to be ready with the most advanced process technologies when the high-performance computing market pushes the envelope for next generation cloud computing, artificial intelligence, and machine learning applications,” said President and CEO Johnny Shen.
Alchip also said that its first 4nm test chip, targeting TSMC’s N4P process technology, will be taped out early in August. Design methodology, design technology and infrastructure and test chips specification had all been finalized at the end of last year.
APLink 4.0 supports N5/N4P die-to-die connection for advanced packaging designs.
