3DIC design refers to semiconductor technology where multiple integrated circuits (ICs) are stacked vertically within a single package. This approach uses through-silicon vias (TSVs) and hybrid bonding to integrate the stacked chips, enabling faster data transfer, reduced power consumption, and a smaller footprint compared to traditional two-dimensional designs.
Future designs for these applications will require high performance and efficiency in cloud and networking infrastructure, mobile devices, and graphics processing units (GPUs).
Alchip’s silicon-proven 3DIC design flow has optimised selected 3DIC designs along three critical dimensions: power delivery, die-to-die electrical interconnect, and system-wide thermal characterization.
The 3DIC design flow’s power delivery module encompasses power integrity, power grid design (including through-silicon-via distribution), and power integrity simulation and sign-off capabilities.
Die-to-die electrical interconnect capabilities identify and rectify low clock skew across dies, process variation immunity, noise immunity, data transmission across different power domains, and inter-die setup/hold timing margin. This capability also addresses power-performance-area (PPA) optimised IO cells for clock and data, as well as redundancy strategies.
Alchip’s 3DIC design flow also covers thermal characterization to increase power density, perform 3D non-uniform power mapping, mitigate 3D thermal crosstalk effects, and provide package and system cooling solution modelling.
“Alchip has been collaborating for many years with our EDA, foundry, and OSAT partners to accelerate multi-die designs,” explained Erez Shaizaf, Alchip’s chief technology officer. “Now, that hard work has culminated in providing the high-performance ASIC market with a design flow that cost-efficiently takes on the complexity of next generation 3DIC ASIC designs.”
