Altera launches Stratix V fpgas
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Altera has unveiled the Stratix V fpga family, designed to support high bandwidth communications applications. The family will be manufactured using TSMC's high performance 28nm process.
Paul Ekas, director of component product planning, said: "We are going after asics and assps, so we need to be competitive on bandwidth, but with cost and power consumption advantages. Stratix V breaks the bandwidth barrier with a potential switching capacity of 1.6Tbit/s"
Stratix V is said by Ekas to be a response to demands from the rapidly developing communications market. "Communications bandwidth requirements are growing at 50% a year," he claimed, "but equipment providers are working within fixed footprints, so need more bandwidth from the same area of silicon. Wired comms is moving to 100G, with 400G on the horizon, and broadcast is moving to high definition." Other markets noted by Ekas include military and storage.
There will be four variants within the family – GT, GS, GX and E. The GT range, which features Altera's 28Gbit/s transceivers, will be targeted at applications where communications bandwidths are typically in excess of 100Gbit/s. The GX range, intended for use with less bandwidth intensive applications, will feature transceivers handling up to 12.5Gbit/s. The GS range, which also features 12.5Gbit/s transceivers, is designed for dsp intensive applications, while the E range is a logic only variant designed for emulation, asic prototyping and similar tasks.
Six members of the GX range have been announced initially, along with two GS parts. The GX range will offer devices with up to 536,000 logic elements (LEs) and the top of the range 5SGSB7 will also feature 66 12.5Gbit/s transceivers, more than 5Mbit of memory in the shape of 2500 20k blocks, 6.5Mbit of memory logic array blocks (MLAB) and 738 18x18bit MACs.
Samples are planned for Q1 2011, but no date has been announced for volume production. HardCopy V devices will also be available at some future date.
