Altera takes fpgas to 40nm

Produced on TSMC’s 40nm process, Stratix IV fpgas feature up to 680,000 logic elements – twice the size of the largest member of the Stratix III range. Meanwhile, Altera has also announced the HardCopy IV family – the asic equivalent of the Stratix IV fpgas. With densities equivalent to those of Stratix IV, the family offers up to 13.3million gates. Paul Hollingworth, senior director of Altera’s HardCopy product group, pictured, said the company had been working for more than three years with TSMC on the 40nm process. “We’ve created nine test chips which has accelerated getting the process up and running. In one 500m transistor test chip, we took a complete Stratix III fpga and mapped it to 40nm. That’s given us a lot of information to tune the process so we can hit the targets when we move to production.” Two Stratix IV variants will be available: the E range, with memory and dsp resources; and the GX range, focused on transceivers. In the latter range, devices with up to 48 8.5Gbit/s transceivers can be supplied. Releasing both fpga and asic implementations simultaneously is said by Altera to allow companies to design with high volume in mind. “Customers want to work with fpgas and asics as soon as possible, so it makes sense to announce both families together.”