Altera set to move fpga technology closer to assp market

Altera believes the move to 28nm fpgas must be accompanied by a radical change in philosophy and is planning to include Hardcopy blocks, partial reconfiguration and 28Gbit/s transceivers in forthcoming devices. The move is set to take fpgas even closer to the assp market. Embedded Hardcopy blocks will allow standard or logic intensive functions – such as interface protocols and application specific functions – to be hardened. These blocks are likely to occupy up to 20% of the die area, bringing a performance boost of up to 20 times. Greenfield said: "Using this approach in fpgas brings advantages, but it will not be as fast as standard cell asics. However, it brings enough performance." Partial reconfiguration will allow blocks as small as two or three LABs – some 20 or 30 Logic Elements – to be repurposed while the fpga continues to operate. The approach takes advantage of Altera's incremental configuration technology, which has been developed from earlier block based design techniques. Although reconfiguration times for the blocks could be as little as 100µs, said Greenfield, reconfiguring the fpga as a whole is likely to take 5s. Meanwhile, Altera has developed transceivers capable of supporting data rates of 28Gbit/s. According to Greenfield, currently 10Gbit/s technology consumes 220mW per channel. For an 800Gbit/s transceiver on 40nm technology, this would give an overall consumption of 17W. The same throughput can be accommodated using 32 transceivers running at 25Gbit/s, each consuming 200mW/channel. On a 28nm process, this equates to a power dissipation of 6.4W. Devices featuring these developments are expected to become available in 2011.