Versal Premium Series Gen 2 is the FPGA industry’s first devices featuring Compute Express Link (CXL) 3.1 and PCIe Gen6 as well as LPDDR5X memory support in hard IP.1
These next-generation interface and memory technologies access and move data rapidly and efficiently between processors and accelerators - CXL 3.1 and LPDDR5X help unlock memory resources faster to address the real-time processing and storage demands of data-intensive applications.
AMD supports CXL, an open industry-standard interconnect between processors and devices such as FPGA-based accelerators, and with CXL 3.1 and PCIe Gen6 the Versal Premium Gen 2 devices will enable high-bandwidth host CPU-to-accelerator connectivity.
PCIe Gen6 offers a 2-4X faster line rate compared to many competing FPGAs with PCIe Gen4 or Gen5 support, while CXL 3.1 running PCIe Gen6 provides double the bandwidth with CXL 2.13 at similar latencies, as well as enhanced fabric and coherency capabilities.
By pairing Versal Premium Series Gen 2 with AMD EPYC CPUs, system architects will also be able to leverage the latest AMD FPGA-based device connected via CXL or PCIe to a high-performance CPU, accelerating data-intensive applications and meeting rapid data growth demands. CXL also brings an additional benefit of memory coherency to help enable true heterogeneous, accelerated computing.
AMD Versal Premium Series Gen 2 adaptive SoCs accelerate memory bandwidth for faster data transfers and real-time responsiveness, offering the fastest LPDDR5X memory connectivity currently available at up to 8533 Mb/s.
This ultra-fast, enhanced DDR memory enables up to 2.7X faster host connectivity over comparable competitive devices with LPDDR4/5 memory.4
Connectivity to CXL memory expansion modules enable up to 2.7X more total bandwidth than LPDDR5X memory alone. As a result, the Versal Premium Series Gen 2 allows for scalable memory pooling and extension for multiple accelerators, optimising memory utilization and increasing bandwidth and capacity.
By dynamically allocating a memory pool for multiple devices, Versal Premium Series Gen 2 adaptive SoCs are designed to improve memory utilisation in a Multi-Headed Single Logic Device (MH-SLD), allowing it to operate without a fabric or switch, while supporting up to two CXL hosts.
Enhanced security features help transfer data quickly and securely, both in transit and at rest. It is the industry’s first FPGA device to feature support for integrated PCIe Integrity and Data Encryption (IDE) in hard IP. Inline encryption built into hard DDR memory controllers helps secure data at rest, while 400G High-Speed Crypto Engines help the device secure user data at up to 2X faster line rates, enabling faster secure data transactions.
According to AMD, Versal Premium Series Gen 2 development tools are expected to be available in Q2 2025, followed by the availability of silicon samples by early 2026.
Production shipments are expected to begin in the second half of 2026.
