The Andes QiLai RISC-V platform is a development board with a QiLai SoC featuring the Andes’ RISC-V processor IPs along with Arteris FlexNoC interconnect IP used for on-chip connectivity.
The QiLai SoC integrates the Andes 64-bit AX45MP multiprocessor (four cores in a cluster) running at 2.2 GHz and the NX27V vector processor running at 1.5 GHz, using Arteris network-on-chip (NoC) interconnect IP with subsystems for PCIe, DDR, SRAM and General Purpose IO using the AMBA AXI protocol.
The supporting software includes the OpenSUSE Linux distribution, AndeSight toolchains, AndeSoft software stacks and AndesAIRE NN SDK to convert AI/ML models to executables.
“Even though AndesCore AX45MP and NX27V processors are widely used, we are still pleased to see the QiLai SoC achieve first time right on new projects," said Dr. Charlie Su, Andes Technology’s president and CTO. "Arteris NoC IP was the obvious choice and the QiLai platform enhances the rapid development and assessment of RISC-V software, accelerating the expansion of the RISC-V ecosystem."
"We are excited to partner with Andes Technology and support the QiLai platform interoperability to further accelerate RISC-V technology mainstream adoption," said Michal Siwinski, chief marketing officer at Arteris. "Our collaboration supports our mission to be the catalyst for SoC innovation so our mutual customers can focus on efficiently creating tomorrow’s breakthroughs."
Arteris’ FlexNoC non-coherent NoC IP and Ncore cache-coherent NoC IP enable scalable, low latency and power-efficient on-chip communication delivering enhanced performance in complex SoC designs.
The technology facilitates the integration of high-performance, low-power CPU IPs, enhancing system functionality and interoperability, especially within the growing RISC-V ecosystem.
This configurable and adaptable interconnect solution seamlessly interfaces with various components to mitigate risks and expedite time to market and by connecting well-tested CPU IP blocks, system designers can leverage Arteris NoC IPs to enhance the reliability and quality of next-generation SoCs.
