The QiLai SoC chip includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. The AndesCore AX45MP superscalar multicore contains a 2MB Level-2 cache, a coherence manger to manage Level-1 cache coherence, and a MMU (Memory Management Unit) for Linux based applications.
The AndesCore NX27V vector processor with 512KB data cache supports a full range of RISC-V standard data types and Andes-enhanced data types which have been optimised for AI workloads. It also contains an efficient scalar unit and an out-of-order Vector Processing Unit (VPU) with 512-bit vector length (VLEN) and 512-bit data path width (DLEN), capable of generating up to 4 512-bit results per cycle.
The NX27V can cooperate with the AX45MP cluster and make QiLai a heterogeneous software development platform where a Linux SMP system and an RTOS or bare-metal system can run simultaneously. The AX45MP and NX27V can run up to 2.2 GHz and 1.5GHz respectively, and the total power consumption of the QiLai SoC is around 5W when running at its full speed.
The new Voyager development board has a 9.6” x 9.6” Micro ATX form factor and includes a QiLai SoC, 16GB of DDR4 SIMM socket, JTAG debugger, USB to UART bridge, I2S Audio Codec, 16Mb SPI Flash for boot code, SD card socket, and several PCIe Gen4 slots that can bridge to many external devices such as GPU card and SSD.
The supporting software includes the OpenSUSE Linux distribution, AndeSight toolchains, AndeSoft software stacks, and AndesAIRE NN SDK to convert AI/ML models to executables running on the NX27V vector processor.
“We are excited to announce the QiLai SoC which integrates our widely-adopted AndesCore AX45MP multicore and NX27V vector processor,” said Frankwell Lin, Andes Chairman and CEO. “These two processors have been licensed and silicon-proven by many customers though we are still pleased to see them working on our own silicon in the first cut. Manufactured at TSMC advanced 7nm process technology, the QiLai SoC and the Voyager development board demonstrate our commitment to enable the RISC-V software development in real time. Andes will keep its pure-play IP provider position, not going into chip business, this project is a response to provide better processor IP evaluation and application development purpose and is an excellent resulting fruit from Andes GDR movement in 2021.”
“Andes has been asked by many partners and software developers for silicon-based platforms, where they can develop software for RISC-V more efficiently,” said Dr. Charlie Su, Andes President and CTO. “The Voyager board with the QiLai SoC is our response to that request and a great step towards enabling fast development and evaluation of a wide range of software for RISC-V, and further helps expand the RISC-V ecosystem.”
