Using the Cadence System-Level Verification IP (System VIP), customers developing complex hyperscale, automotive, mobile and consumer chips will be able to improve chip-level verification efficiency by up to 10X.
The Cadence System VIP solution takes IP-level verification automation and brings it to the chip level. Tests created using System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to post-silicon bring-up.
Cadence System VIP consists of four new tools and libraries:
- System Testbench Generator: Allows users to automatically generate SoC testbenches with complex memory, cache, interface and bus configurations
- System Traffic Libraries: Provide users with a rich portfolio of pre-defined tests that can be plugged into a System VIP testbench
- System Performance Analyzer: Offers comprehensive performance analysis reporting and visualization for memory subsystems, interconnects and peripherals
- System Verification Scoreboard: Provides comprehensive data and cache-coherency checks across coherent interconnects, memories and peripherals.
“Verification challenges increase exponentially as the number and complexity of integrated IP blocks on an SoC grow,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “Our Cadence System VIP solution dramatically improves verification throughput by automating some of today’s most critical labour-intensive chip-level verification challenges.”
The Cadence System VIP tool suite is part of the broader Cadence Verification Suite which is comprised of core engines and smart verification technologies that increase verification throughput and design quality, fulfilling verification requirements for a wide variety of applications and vertical segments.
