These latest VIP offerings are intended to empower users looking to develop their next-generation automotive, hyperscale data centre and mobile SoCs and microcontrollers while keeping pace with the latest industry standards.
These include Arm AMBA 5 CHI-f, Universal Chiplet Interconnect Express (UCIe), GDDR7, DDR5 DIMM, MIPI A-PHY and SoundWire I3S, and USB4 2.0 interfaces.
The new Cadence VIP provides a comprehensive verification solution for the most complex protocols and customers will have access to a consistent application programming interface (API) across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption.
The VIP support multiple application areas and specifications, including:
- Hyperscale data centre:
- UCIe
- AMBA 5 CHI-f
- DTI
- Latest version of DDR5 DIMM
- Automotive:
- MIPI A-PHY 1.1
- CAN XL
- Flash ONFI 5.1
- Consumer and mobile:
- USB4 2.0
- GDDR7
- MIPI SoundWire I3S (SWI3S)
- Latest version of LPDDR
- DFI
- HDMI 2.1
All of these VIP solutions include Cadence TripleCheck technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification.
The new VIP also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers. Using the expanded System VIP portfolio, Cadence said that users could experience up to 10X efficiency improvements compared to a manual process for SoC verification.
“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “With these 13 new VIP, Cadence is offering customers solutions to ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”
