The programme is one of six within DARPA’s Electronics Resurgence Initiative (ERI) to use advanced machine learning techniques to develop a unified platform for a fully integrated, intelligent design flow for systems on chip (SoCs), systems in package (SiPs) and printed circuit boards (PCBs).
The ERI investments are intended to help create a more automated electronics design capability that will benefit the aerospace/defence ecosystem, as well as the commercial needs of the electronics industry.
Cadence has created the Machine learning-driven Automatic Generation of Electronic Systems Through Intelligent Collaboration (MAGESTIC) research and development program to address the needs of this four-year contract.
This programme will create a foundation for system design by introducing greater autonomy within the design process and developing design-intent-driven products. The Cadence-led team includes the Carnegie Mellon University and NVIDIA, two machine learning leaders.
“We’ve been leading the industry in the development, deployment and support of electronic design flows that use machine learning, analytics and optimisation technologies. This program will accelerate our roadmap toward realising intelligent design flows for the next big leap in design productivity,” said Anirudh Devgan, president of Cadence. “This program will set the stage for enhancing the entire span of our analogue, digital, verification, package and PCB EDA technologies, providing our customers with the most advanced system design enablement solutions.”
The DARPA ERI programmes look to address impending engineering and economics challenges that, if left unanswered, could undermine what has been a relentless half-century run of progress in microelectronics technology. It is now clear that the design work and fabrication required to keep pace in microelectronics is becoming increasingly difficult and expensive.
The MAGESTIC program aims to address:
- Advancing the state of the art in machine learning to develop algorithms that optimise performance
- Extending support for advanced CMOS process nodes including 7nm and below, as well as larger process nodes
- Automating the routing and tuning of devices to improve reliability, circuit performance, and resilience
- Demonstrating improved power, performance and area (PPA) utilizing machine learning, analytics, and optimisation
- Staging the introductions of the technology, allowing the system to learn from the users and allowing users to gain an understanding of how to best leverage the tools to achieve desired results.
The programme will also help to extend Cadence’s work in employing cloud-based design systems to handle large-scale distributed processing to speed design efforts.
