Cadence tapes out 14nm test chip, with help from ARM and IBM
Cadence has announced the tape out of a new 14nm test chip, featuring an ARM Cortex-M0 processor implemented using IBM's FinFET process technology.
The chip, developed as part of a multiyear agreement between the three technology firms, is designed to offer significant reductions in power consumption and aimed at validating the building blocks of foundation IP for 14nm design.
Chi-Ping Hsu, senior vice president of Cadence's silicon realisation group (pictured), said: "This chip represents a major milestone for advanced node process technology, achieved through tight collaboration among experts at the three companies. FinFET designs offer significant advantages to the design community, but also require advanced foundry support, IP and EDA technology to meet the considerable challenges.
"Cadence, IBM and ARM are collaborating to address these challenges and develop an ecosystem that can support 14nm FinFET development for a broad range of production designs."
