GlobalFoundries tapes out 20nm test chip
GlobalFoundries has taped out a 20nm test chip using flows from eda vendors Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys.
"This success is a major achievement toward market readiness of our newest process, and we will continue to enhance the design enablement support available for it," said Mojy Chian, pictured, senior vp of design enablement at GlobalFoundries.
The test chip is supported by library preparation steps for double patterning technology, a complex lithography approach, placement, clock tree synthesis, hold fixing, routing and post route optimisation.
According to GlobalFoundries, the flow will also demonstrate foundry support for extraction, static timing analysis and physical verification. The company will make the design, libraries, and complete vendor flow scripts available to customers who wish to evaluate 20nm technology.
