The family supports a wide range of demands including long reach plus (LR+), long reach (LR), medium reach (MR), extreme short reach plus (XSR+), and extreme short reach (XSR) which are required by applications including compute, switching, AI, machine learning, security, and optical deployments.
Commenting Jim Bartenslager, Associate Vice President of Business Development for IP Products, said, “Credo’s advanced mixed signal and DSP 112G PAM4 SerDes architectures were developed and proven on the TSMC 12nm process technology for Credo’s complete family of connectivity solutions for both copper and optical applications. We have ported our unique, purpose-built SerDes technology to the TSMC N5 and N4 processes to allow our partners and customers to seamlessly integrate our industry leading 112G PAM4 IP into larger scale monolithic and multi-chip-module ASICs.”
“Our latest collaboration with Credo makes it easy for customers to benefit from the significant power and performance improvements of TSMC’s advanced N5 and N4 processes,” said Dan Kochpatcharin, Director of the Design Infrastructure Management Division at TSMC. “We look forward to working closely with Credo to address the design challenges for rapid advancement of applications in compute, switching, AI, and machine learning.”
Credo’s software programmable innovations will allow architects to optimise power and performance on a lane-by-lane basis, improving system level performance.
These 112G PAM4 SerDes IP were designed to meet the data needs of high-speed, data-intensive applications and early access design customers are able to engage immediately with Credo.
Production, silicon validation, design kit of these 112G SerDes for multiple TSMC processes from N16 to N4 are available on TSMC-Online.
