The new architecture offers 25% power savings, 40% area reduction and better design margins over the second-generation architecture, and looks to address the increasing needs for higher performance and power efficiency in modern next-generation cloud data centres.
Cadence has enabled different variances of PAM4 SerDes supporting XSR, VSR, MR and LR interconnect standards and through a combination of design wins and collaborations with leading hyperscale and data centre customers, has been able to incorporate specific enhancements in the third-generation product and currently has N5 test chips in-house that are undergoing characterization.
Cadence has been working closely with early adopter customers on deploying the new 112G-LR SerDes IP in their 5nm SoC development and is now ready to engage more broadly with customers to enable next-generation designs.
With the improved architecture, Cadence is now able to offer enhanced DSP with multiple floating decision feedback equalization (DFE) taps to enable more robust performance. The 1-112G gapless data rate support provides much improved I/O flexibility for chip-to-chip connectivity for AI/ML accelerator SoCs. In addition, a 10X improvement in supply noise immunity greatly eases the SoC power delivery network (PDN) design.
Commenting Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence said, “Our close collaborations with leading hyperscale and data centre customers have given us the insights into the stringent industry requirements, resulting in a new design with enhanced architecture that offers improvements on all the key parameters for 112G SerDes and network switches.
"Our 112G-LR SerDes solution on TSMC’s N5 process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centres, and customers can also enjoy the benefits associated with the TSMC N5 process technology.”
