Diamond project claims major advance in chip verification and test
2 mins read
An EU research project claims to have developed a means to speed fault testing and verification of chips. The approach to detecting and solving errors is said to save money and lower the cost of electronic equipment and devices.
In recent years, says the project, numerous test and verification approaches have emerged. But, while they are good at identifying the presence of faults, they are usually unable to pin point the root cause of an error.
"It is not helpful for the designer to merely know that the chip is not working," said Dr Jaan Raik, a professor of digital systems verification at the Department of Computer Engineering of Tallinn University of Technology in Estonia. "It is necessary also to locate the fault and, ultimately, to correct it. Relatively little attention has been paid to the latter tasks."
Over the last three years, a consortium of universities and technology companies formed the DIAMOND project to develop innovative models and technology to test, detect, verify and fix chip errors. Their work is said to represent a 'major leap forward' for the semiconductor industry.
According to the DIAMOND project, a modern chip design project costs around €60million, but says automating the error detection and correction process could save €15m.
Dr Raik says the project's work has benefits. "First, a holistic model for different types of faults was developed. Based on this model, the same localisation engines can be applied to design errors, soft errors and defects. Second, more efficient automated localisation and correction methods were developed. Particular stress was put on system level approaches where previous research work has been inadequate. Finally, post silicon in situ debug approaches were developed. Such approaches extend the life time of silicon chips by localising and isolating faulty regions in them."
The team created an open source system level design error localisation and correction system called Forensic. Errors at the register transfer level were handled using a design elaboration system called zamiaCAD, whyile a post silicon fault management system to extend the lifetime of future chips was also developed.
"At the system level, Forensic was able to correct 60% of the benchmark designs, compared to 16% with previous tools," said Dr Raik. "At the RTL, we performed a case study on a real processor design. We cooperated with a design team at TU Ilmenau who provided us with documented bug cases. The DIAMOND methods located all bugs in a couple of minutes, versus several hours needed for manual localisation."
Three project partners are now preparing to launch BASTION, a follow up project to further enhance the fault detection technology. IBM has filed two patents on technologies developed in DIAMOND and is exploiting the results internally, while Ericsson is applying the fault management technology in product developments.
