The CEVA-XC5 and CEVA-XC8 DSP vector processors are the smallest and most power-efficient members of the CEVA-XC architecture, supporting a range of emerging cellular protocols, including LTE MTC Cat-1, Cat-0 or Cat-M. The cores also work with low power wide area network (LPWAN) standards such as LoRA, SigFox and Ingenu.
In particular, CEVA sees opportunities in the cellular sector. “There were 250million cellular connections in 2014,” said Emmanuel Gresset, business development manager, “and this is expected to grow to 2billion by 2020, with the transition to LET and refarming pressure.”
CEVA sees growing demand for such cores. Gresset said the challenge was to develop a core with extremely low power consumption and low cost. “This required an efficient compute system where the PHY/protocol can run on the same processor to minimise latency and reduce time to market. Compared with previous cores, these consume 70% less dynamic power and are 40% smaller.”
The cores feature eight way VLIW vector units. The single unit in the XC5 runs 16MACs per cycle, with the twin units in the XC8 double this to 32MACs/cycle. Each has a four way associative cache, along with a power scaling unit (PSU) which Gresset pointed out is ‘key for IoT applications’. “It allows users to take advantage of LTE Cat-0 and Cat-M.”
The PSU supports multiple clock sources, with the ability to shut down blocks. It also manages the memory subsystem and the Level 1 caches. Multiple voltage domains are also supported. According to CEVA, the PSU can reduce dynamic power consumption during Cat-0 extended discontinuous reception and power saving modes by up to 70%.
Gresset noted the cores are already being designed in by lead customers and added other companies are studying them. “There has been huge demand for cores like these,” he concluded, “and I believe they will be very popular for low end IoT applications.”
