Initial silicon for characterization is expected in Q1 2025.
The high-performance interconnect solution has been developed to support up to 40Gbps bandwidth at unprecedented power levels, as was recently demonstrated at the OCP Global Summit. It utilises advanced packaging micro bumps at 45-micron pitch and offers what is said to be the industry’s lowest power density.
Fully compatible with the UCIe standard, it further confirms Eliyan’s ability to extend die-to-die and die-to-memory connectivity performance on standard as well as advanced packaging.
Eliyan will use the technology for building its custom High Bandwidth Memory (HBM) base dies and offer it as IP to enable ASIC disaggregation approaches that leverage chiplets. The performance and power of the solution allows it to support multi-die designs that address the memory and IO walls common in GenAI subsystem-level designs.
“Samsung Electronics is a recognised leader in advanced foundry logic process for GenAI and HBM chips used in tomorrow’s data centres,” said Paul Cho, Corporate EVP of Products and Solutions Planning at Samsung Electronics. “Eliyan’s technology enables Samsung’s customers to fully leverage its process technologies and memory products to their fullest potential.”
“We see custom HBM4 base die as a critical piece of all future AI systems for both training and inference of GenAI/LLMs. Our NuLink PHY technology meets the stringent power and thermal density requirements to enable the highest performance connectivity between XPUs and HBMs and provide the needed reliability and scalability,” said Eliyan’s co-founder Patrick Soheili.
