The latest PHY supports both advanced and standard chiplet packaging with an aggregate throughput exceeding 100 Tbps while achieving industry-leading silicon area footprint and power consumption.
The BlueLynx D2D subsystem IP enables chip architects to meet the bandwidth density and environmental robustness necessary to ensure successful production deployment while preserving use case flexibility.
Using Samsung Foundry's SF4X 4nm advanced process, the BlueLynx PHY supports both standard 2D and advanced 2.5D packages and enables system designers to seamlessly change packaging technologies in current and future implementations.
Customer deliveries started in 2024 with silicon characterization in both advanced and standard packaging applications expected in early Q2 2025.
Blue Cheetah's IP solutions are customisable and are used in AI/ML, high-performance computing, networking, and mobile applications in advanced process nodes.
BlueLynx PHY solutions support Universal Chiplet Interconnect Express (UCIe) and the Open Compute Project (OCP) Bunch of Wires (BoW) interfaces. An optional link layer connects to on-die buses/Networks-on-Chip (NoCs) using various standards, including AXI4, AXI5 Lite, ACE, and CHI.
"Samsung Electronics offers a robust portfolio of advanced foundry process technologies optimised for generative AI and HPC chips," said Ben Hyo Gyuem Rhew, vice president and the head of the IP Development Team at Samsung Electronics. "Blue Cheetah's BlueLynx PHY technology enables our customers to maximise their chiplet-based design performance with accelerated time to market using silicon-proven IP."
"Die-to-die interconnect technology is a crucial component of any chiplet design," said Blue Cheetah's CEO and co-founder, Elad Alon. "We are excited to be able to offer our customisable state-of-the-art chiplet interconnect solutions on Samsung's advanced logic process nodes."
