In what is described as a significant milestone in high-performance computing the EPAC1.5 is a collection of RISC-V based accelerators that have been designed to push the boundaries of acceleration technologies.
This test-chip looks to showcases three distinct approaches to acceleration:
- General purpose CPU with dedicated vector unit (VPU)
- Many-core stencil/machine learning accelerator (STX)
- General Purpose CPU supporting variable precision (VRP)
The EPAC 1.5 design contains vector processing micro-tiles (VPU) composed of the Avispado RISC-V core designed by SemiDynamics and a vector processing unit that’s been designed by the Barcelona Supercomputing Center and the University of Zagreb.
Additional micro-tiles contain distributed Home Nodes (HN) and L2 cache slices (L2), designed respectively by Chalmers and FORTH-ICS, that provide a coherent view of the shared memory subsystem.
The chip also includes the Stencil and Tensor accelerator (STX) designed by ETH Zürich and Fraunhofer IIS and the variable precision processor (VRP) designed by CEA.
All accelerators are interconnected with a very high-speed network on chip with multiple crosspoints (XP) and an off-chip link using SERDES technology from EXTOLL.
The physical design was performed by Fraunhofer IIS using Globalfoundries 22FDX low-power technology. The chip is 27mm2 with 0.3 billion transistors and is hosted on a daughtercard designed by E4.
The complex bring-up and Linux boot process was carried out at FORTH-ICS, Heraklion, Crete, Greece, and EXTOLL, Mannheim, Germany.
The EPI team demonstrated Linux boot (Ubuntu 22.04 LTS) in both command-line and graphical user interface modes and were able to seamlessly integrate the execution of High-Performance Computing (HPC) kernels, harnessing the power of the vector processing unit within the vector accelerator.
“Seeing a standard Linux distribution’s GUI boot on a chip developed through collaborative efforts within the European Union consortium has been nothing short of thrilling,” declared Filippo Mantovani, the coordinator of the EPAC effort at BSC.
Roger Espasa, founder and CEO of Semidynamics, added, “The Avispado core by Semidynamics is an integral part of EPAC, and we take immense pride in our role within this successful EU endeavour. Semidynamics’ development of Avispado has been advanced by EPI funding, propelling the EPAC architecture forward over the past four years.”
The successful bring-up of EPAC 1.5 is a major step in the development of the EPI common platform, showcasing the variety of accelerators that can be integrated in future European supercomputers to efficiently address a wide range of compute problems.
