The collaboration will see MachineWare lend its support by integrating the AX45MPV into their SIM-V high-performance simulation solution. This integration will support software developers, enabling them to efficiently handle intricate AI and Linux stack related workloads.
The aim is to create a platform that streamlines development, testing, and software verification well in advance of physical prototypes emerging from the fabrication process.
With Machine Ware’s SIM-V, developers can thoroughly test and verify their RISC-V-based systems and software applications long before first prototypes are back from the fab. At its core, SIM-V provides a fast Instruction Set Simulator (ISS) that supports all RISC-V standard extensions.
One key attribute of the SIM-V is its user-friendly customisability. Through a straightforward extension SDK, developers can integrate custom instructions, registers, and other elements into the simulator to get instant feedback on their design choices.
The AndesCore AX45MPV is a 64-bit 8-stage dual-issue multicore RISC-V vector processor. It incorporates RISC-V GCBP* (*P is a draft version) extensions and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses.
In addition, it can be configured to up to eight cores with a cache coherence manager and up to 8MB shared L2 cache memory in a cluster. The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN).
The device is intended for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing.
Commenting Lukas Jünger, Managing Director at MachineWare said, “The incorporation of the AX45MPV model enables our common customers to develop RISC-V Linux and AI software stacks and verify their functionality in minutes. This will eliminate bugs and elevate software quality all the while making the overall development process more efficient.”
"Andes’ collaboration with MachineWare is consistent with our continuous effort to broaden RISC-V ecosystem for easy adoption of high-performance simulation tools," said Samuel Chiang, deputy marketing director of Andes Technology. "We are excited to come together with MachineWare to drive the expansion of the RISC-V ecosystem. And we believe RISC-V's instruction set architecture will increase innovation and has the potential to transform the AI market."
