The ASIC, known as SOC2, was designed and taped out in a TSMC 16nm technology by Bar-Ilan University SoC Lab, as part of the HiPer Consortium, backed by the Israeli Innovation Authority (IIA) and enables more flexible and changeable instruction sets to meet demanding and changing processing workloads.
"The ability to add custom instructions to minimise power and maximise performance efficiency of embedded processors has been around for decades,” said Andy Jaros, VP of Sales and Marketing for Flex Logix’s eFPGA IP. “The ISA extension capability works great for targeted applications, but it can be a costly solution when the application changes or new use cases need different instructions requiring a new chip to be developed. By working with CEVA and the HiPer Consortium, the SOC2 proves that reconfigurable computing is here with a DSP Instruction Set Architecture (ISA) that can be adapted to different workloads with custom hard-wired instructions that can be changed at any time in the future.”
According to Erez Bar-Niv, CEVA's Chief Technology Officer, “The SOC2 contains two processing clusters, each with two CEVA-X2 DSP cores and an EFLX eFPGA for programming and executing DSP instructions extensions, connected using the CEVA-Xtend mechanism. Flex Logix and CEVA’s mutual customers can now utilise custom instructions to extract more value from their ASIC by being able to target different DSP applications on top of communication and sound with a customizable ISA post manufacturing.”
The EFLX eFPGA can be used anywhere in an ASIC architecture. In addition to the ISA extension interface, EFLX has been used for packet processing, security, encryption, IO muxes, and general-purpose algorithm acceleration.
Using EFLX, developers can implement an eFPGA from a few thousand LUTs to over a million LUTs with performance and density per square millimetre similar to FPGAs in the same process generation. EFLX eFPGA is modular so arrays can be spread throughout the chip, can have all-logic or be heavy-DSP, and can integrate RAM.
EFLX eFPGA is available in 12, 16, 22, 28 and 40 nm process nodes and is in development at 7nm with more advanced nodes planned for future release.
