The technology is designed to automate the generation of reusable integrated circuits (IC) layout blocks and it is intended to produce a layout according to the IC’s description and its goal is to save time during the design of a microchip.
The intellectual property block can be used as a black-box to be inserted within existing or future IC projects, as a plug-and-play unit, with the goal of enabling time saving by avoiding entire re-design process.
The patent was filed at the end of September and received an application ID: 17953378.
Using reusable IPs is an efficient method to quickly design a System on Chip (SoC) which contains core blocks that perform different tasks such as internal storage, central processing unit (CPU), and input/output ports.
Modern SoCs also may include AI and other complex blocks to enable advanced capabilities. Using reusable, pre-designed IP cores/blocks is, consequently, becoming more crucial to minimise the entire IC’s design time.
GBT’s non-provisional patent application describes a system that has the goal of automatically generating IC layout IP blocks, reading defined process design rules, constraints and the microchip’s specifications.
The goal of this IP is to reduce IC project’s design and costs, as well as the silicon space occupied by large systems. GBT plans to continue its research and development efforts in this area of enabling efficient microchip’s design projects and, in turn, reducing their time-to-market factor.
“By reusing IP blocks, we believe we can significantly shorten microchip’s projects design time. Instead of re-design, the on-chip units that are in charge of known features are simply used as plug-and-play, readymade chips. For example, if a UBS3 feature is needed within a microchip, we simply can use a readymade block that was already designed on another chip. Our non-provisional patent application seeks to protect a computer programme method and system that will be used to automatically generate sub-units of microchips according to specifications and selected manufacturing process rules.
“The best example is an SoC or Systems on Chip. A SoC is an integrated circuit system that includes sub-systems on it. Each sub-system is an IP block that is connected with the others to create an entire functional system. Many of these blocks can be reused for future projects. An example of IP blocks are USB ports, HDMI, graphic processing units, wireless units and more. Our technology can read any circuit’s specifications, the process rules and constraints and automatically generate the IC’s layout block with a click of a button. This block can be used later for many other projects. If another circuit is needed, then the technology can easily generate it from scratch.
“We believe an automatic generation of IP layout blocks, that can be reused unlimited times across SOC designs, would provide an advantage for fabless IC design firms as we believe our software will allow the user to design their ICs faster, with more functionalities, and lower cost, especially with advanced nanometre projects. Ultimately, our goal is to fully develop this software to allow for the reduction of IC’s project’s time-to-market, reducing design efforts and cost and creating a whole world of possibilities in the electronics arena,” explained Danny Rittman, the company’s CTO.
