GlobalFoundries announces 28nm design flow

Developed in collaboration with EDA/IP partners including Synopsys, Mentor, Magma, Apache, Cadence and ARM, the flow is based on the company's 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG). GloFo says it includes superior design rule checking called DRC+, which uses two dimensional, shape based pattern matching to enable up to 100fold speed improvement in identifying complex manufacturing issues. "Many of the world's top IC designers are using our 28nm technology to deliver tomorrow's most innovative mobile and consumer devices," said Mojy Chian, senior vice president of design enablement at GlobalFoundries. "By collaborating closely with our partners in the EDA/IP ecosystem, we are giving customers confidence that their designs will be brought to life smoothly and in time to meet their critical market requirements." According to GloFo, the new signoff ready flows have been developed with recognition of the need for silicon validation to ensure 'first time right' silicon success. The company says customers will now be able to produce signoff ready 28nm designs using the 'industry's most advanced' set of synthesis, place and route, sign off and DFM tools, tool scripts and methodologies. "The ARM Artisan physical IP platform offers designers a wide range of implementation options to achieve their low power requirements and processor performance goals," said Simon Segars, pictured, executive vice president and general manager, Physical IP Division, ARM. "Qualifying EDA technology with Artisan physical IP and tuning the IP for GlobalFoundries' manufacturing process is an important element of assuring these platforms support the diverse SoC implementation flows used across the fabless semiconductor industry."