Goepel unveils 'whole new' test platform

According Thomas Wenzel, director of Goepel electronic's JTAG/Boundary Scan Division, the ChipVORX models enable high speed access tests for any kind of RAM devices with full automation of the test development workflow. "In particular for the access test of the latest generation of ddr-sdram devices, traditional boundary scan practice is often problematic due to the stringent timing requirements of such memory devices," he said. "The new ChipVORX solution utilising fpga embedded instruments provides a well suited supplement. Thanks to an exclusive cooperation with our partner Testonica we were able to completely integrate the new methodology into the automated workflow of our JTAG/boundary scan software platform System Cascon, offering our customers another mature test strategy to work with." Artur Jutman, director of Testonica Lab added: "We see ChipVORX as a whole new test platform that is tightly integrated with traditional boundary scan, opening up a new horizon for testability improvements. The enormous flexibility provided by fpgas enables a range of test solutions that are limited only by the imagination. The new RAM Access Test IP is another milestone on the path towards an advanced JTAG controlled embedded instrumentation platform." Goepel says that the complete system integration of ChipVORX IP, enables the recognition of structural connections between the RAM targets and the fpga as well as the test program generation and - in the case of detected defects - the pin level diagnostics are fully automated. The test itself is based on access through a standard IEEE 1149.1 Test Access Port and can be executed on any System Cascon run time station without additional options. ChipVORX models for RAM Access Test are currently available for all Altera and Xilinx fpga families, with others in development. According to Goepel, the use of ChipVORX IP does not require any background knowledge nor any special fpga tools or recurring IP modifications.