Imperas supports advanced RISC-V processor verification solutions and methodology enabling the transition between issue detection and debug resolution within a unified testbench environment compatible with the leading SystemVerilog EDA tools.
Its solutions offer processor developers a flexible framework for RISC-V processor verification and feature native support for RVVI (RISC-V Verification Interface), so developers can connect a new processor implementation to a testbench and leverage the ecosystem of verification IP. Imperas has also released a set of SystemVerilog functional coverage libraries that will help developers achieve the coverage goals of an extensive RISC-V processor verification plan.
MIPS’ latest RISC-V based processor cores require a level of verification that covers extensive hardware features. Its latest RISC-V innovation, the eVocore P8700 multiprocessor, offers superscalar performance with multi-issue Out-of-Order (OoO) execution and multi-threading, and can scale to 64 clusters, 512 cores and 1,024 harts/threads. In addition, it is an enhanced in-order multiprocessing system combining multi-threading and a highly efficient triple issue pipeline, and is able to scale to 64 clusters, 512 cores and 2,048 harts/threads.
“At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors,” said Don Smith, Vice President Engineering at MIPS. “As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.”
“Since 2010, MIPS core IP deliverables have included the Imperas based ISS, and as a consequence our technology has helped to support many projects in applications such as high-performance wireless communications, networking, automotive and AI applications,” explained Simon Davidmann, CEO at Imperas Software. “With MIPS’ strategic shift to RISC-V, we are pleased to continue our long-standing relationship with new technology and innovation for verification for the latest MIPS RISC-V based Applications-Class processors.”
