Imperas has designed an integrated reference model and simulator as a fixed platform kit to support the growing ecosystem of RISC V. The models are the established reference for RISC V and are now included as a fixed virtual platform as part of the Intel Pathfinder for RISC-V Professional Edition.
RISC-V is an open standard ISA (Instruction Set Architecture) that offers designers new freedoms to configure a custom processor with standard extensions and configuration options plus custom instructions.
Imperas simulation and reference model technology supports the latest RISC-V ratified and close to ratified draft specifications as a full configurable envelope model. A high quality and dependable reference model it was developed for use in hardware verification use cases such as compliance, verification and test development, plus as software development targets for firmware, drivers, OS porting and application development.
The simulator with proprietary just-in-time code-morphing simulation technology can be integrated within other standard EDA environments such as SystemC, SystemVerilog, and well-known simulation/emulation tools from Cadence, Siemens EDA, and Synopsys plus the cloud-based offering from Metrics Technologies.
Imperas RISC-V reference models of many commercial RISC V processor cores are also available via approved EDA distribution partners.
“With all the design freedoms and configurability that RISC-V offers, early software development and architectural analysis is critical for optimised hardware and software co-design,” said Simon Davidmann, CEO at Imperas Software. “We are pleased to work with Intel on the Intel Pathfinder, since this not just helps the design process with a “shift-left” for early software development, it enables the entire industry to innovate with RISC-V and accelerate the time-to-volume schedules.”
Vijay Krishnan, General Manager, RISC-V Ventures from Intel, added, “The availability of Imperas RISC-V reference models for the Professional Edition of Intel Pathfinder for RISC-V further strengthens the tools available to developers as new silicon designs move from concept to production.”
