The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometres.
“Infineon’s breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization,” said Jochen Hanebeck, CEO at Infineon Technologies.
According to Infineon, this innovation will significantly help increase energy efficiency, power density and reliability in power conversion solutions for applications in AI data centres as well as consumer, motor control and computing applications.
By halving the thickness of a wafer it reduces the wafer’s substrate resistance by 50 percent, reducing power loss by more than 15 percent in power systems, compared to solutions based on conventional silicon wafers. For high-end AI server applications, where growing energy demand is driven by higher current levels, this is particularly important in power conversion - here voltages have to be reduced from 230 V to a processor voltage below 1.8 V.
The ultra-thin wafer technology boosts the vertical power delivery design, which is based on vertical Trench MOSFET technology and allows a very close connection to the AI chip processor, reducing power loss and enhancing overall efficiency.
“The new ultra-thin wafer technology drives our ambition to power different AI server configurations from grid to core in the most energy efficient way,” said Adam White, Division President Power & Sensor Systems at Infineon. “As energy demand for AI data centres is rising significantly, energy efficiency gains more and more importance. For Infineon, this is a fast-growing business opportunity. With mid-double-digit growth rates, we expect our AI business to reach one billion euros within the next two years.”
To overcome the technical hurdles in reducing wafer thickness to the order of 20 micrometres, Infineon engineers had to establish an innovative wafer grinding approach, since the metal stack that holds the chip on the wafer is thicker than 20 micrometres. This significantly influences handling and processing the backside of the thin wafer.
Additionally, technical and production-related challenges like wafer bow and wafer separation have a major impact on the backend assembly processes ensuring the stability and first-class robustness of the wafers. The 20-micrometre thin wafer process builds on Infineon’s existing manufacturing expertise and ensures that the new technology can be seamlessly integrated into existing high-volume Si production lines without incurring additional manufacturing complexity, thus guaranteeing the highest possible yield and supply security.
The technology has been qualified and applied in Infineon’s Integrated Smart Power Stages (DC-DC converter) which have already been delivered to first customers.
With the current ramp up of the ultra-thin wafer technology Infineon expects a replacement of the existing conventional wafer technology for low voltage power converters within the next three to four years.
