IP framework expanded with processor and multicore technologies

Among the enhancements are: comprehensive multicore features; high throughput vector floating point processing; and a set of coprocessor engines. Included in the announcement is the MUST multicore system, described as a cache based multicore technology with support for cache coherency, resource sharing and data management. Initially available for the CEVA-XC, MUST supports the integration of multiple CEVA-XC dsp cores in symmetric or asymmetric multiprocessing systems. MUST offers such features as:dynamic scheduling; jardware event based scheduling; task and data driven shared resource management; and advanced memory hierarchy support. Meanwhile, to support the development of multicore SoCs containing ARM processors and multiple CEVA dsps, CEVA has added support for the AXI4 interconnect protocol and AMBA4 ACE cache coherency to the CEVA-XC architecture framework. Alongside floating point support, CEVA has also introduced tightly coupled extension (TCE) coprocessor units that improve device performance. Eran Briman, vice president of marketing, said: "The suite of technologies introduced today will serve to improve the performance, power consumption and time to market for multicore dsp SoC designs targeting wireless applications. The combination of our MUST multicore system technology, vector floating point operation support, support for ARM's latest interconnect protocols and the set of function specific tightly coupled extensions further reinforces our leadership in dsp technologies for communications."