Mentor addresses dummy fill shortfalls
1 min read
Planarity in leading edge chips is becoming more of a problem as process nodes shrink. Traditionally solved through the so called 'dummy fill' approach, planarity now needs a more thorough approach, according to Mentor Graphics.
The company has added new capabilities to its Calibre platform which it claims can now provide a complete solution for the control of thickness variability due to Chemical Mechanical Polishing (CMP) at advanced nodes.
Jean-Marie Brunet, director of product marketing for Mentor's Design for Manufacturing (DFM) group, said that as processes become more complex, designers need three types of model bases analysis tools: critical area analysis; litho pattern checking; and CMP. These tools address, respectively, random defects, systematic lithography issues and systematic 3d variability.
"Systematic defects and CMP problems tend to show up early in a product's ramp," he claimed, "and the DFM tools which are catching these problems are moving from 'nice to have' to something required."
Brunet believes DFM capability is now regarded as a competitive weapon and cited the recent launch by CSR of the UniFi UF6000 range of WiFi chips.
"Calibre tools," he claimed, "are providing CSR with predictable yield, no manufacturing related respins and a more robust design."
From CSR's perspective, vp operations Chris Ladas noted: "CSR is moving to the most advanced process nodes at a very rapid pace, so we're employing sophisticated DFM practices to ensure our designs are more robust over the process window and to eliminate manufacturing surprises late in the development cycle. We're extremely pleased with the results we achieved on our most recent RFCMOS 65nm design, which employed a full range of DFM methods, including Calibre tools."
Calibre includes a CMP simulator with models for leading fabs validated against silicon. It also allows users to create and calibrate their own thickness models.
