“TSMC’s collaboration with design ecosystem partners like Siemens helps our mutual customers remain at the forefront of technology innovation,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “This close partnership provides customers with proven design solutions that allow customers to more fully leverage the significant performance and power efficiency advantages of TSMC’s advanced process technologies.”
Siemens’ Calibre nmPlatform tool for integrated circuit (IC) verification sign-off is now fully certified for TSMC’s most advanced N2 process, including Calibre nmDRC software, Calibre YieldEnhancer software, Calibre PERC software and Calibre nmLVS software – all of which are now in place for the earliest adopters of this advanced new process technology offering from TSMC.
TSMC and Siemens have also collaborated to certify Siemens’ mPower analogue software for transistor-level electromigration and IR drop (EM/IR) sign-off using TSMC’s N4P process. This will allow mutual customers to apply mPower’s EM/IR signoff solution to their next-generation analogue or radio frequency (RF) designs.
Collaboration for Siemens’ Solido Design Environment and Analog FastSPICE TSMC’s N4P, N3E and N2 custom design reference flow (CDRF) works now with Siemens’ Solido Design Environment software for advanced variation-aware verification at high sigma.
In addition, Siemens’ Analog FastSPICE platform for circuit verification of nanometer analogue, RF, mixed-signal, memory, and custom digital circuits has successfully achieved TSMC certification for the foundry’s advanced N5A, N3E, N3P and N2 processes. As part of the CDRF flow for TSMC’s N4P, N3E and N2 processes, Siemens’ Analog FastSPICE platform now supports TSMC’s Reliability Aware Simulation technology, which addresses IC aging and real-time self-heating effects among other advanced reliability features.
Siemens also announced that its Aprisa place and route solution has received TSMC certification for the foundry’s N3E process.
“TSMC’s pace of innovation is remarkable,” said Joe Sawicki, executive vice president, IC-EDA for Siemens Digital Industries Software. “Optimising our EDA solutions for TSMC’s latest processes helps us provide our mutual customers with innovative solutions that satisfy their challenging and rapidly evolving market and business requirements.”
Siemens also revealed significant progress with TSMC in certifying several of its 3DIC solutions for TSMC’s advanced 3DFabric technologies.
TSMC has certified 3Dblox 2.0 with Siemens’ Calibre 3DSTACK software for physical analysis and circuit verification. This certification includes support for inter-chiplet DRC and LVS checks as requirements for TSMC 3DFabric technologies.
In addition, TSMC recently certified an array of Tessent 3DIC solutions including Tessent hierarchical DFT, Tessent Multi-die with enhanced TAPs (test access ports - IEEE 1838 compliant), native flexible parallel port (FPP) support using streaming scan network (SSN) and IEEE 1687 IJTAG network technologies.
Both companies are strengthening their commitments to investing in building 3DIC testing ecosystems under TSMC 3Dblox, which includes known good die (KGD) loopback test and physical aware die-to-die fault detection and diagnosis utilising BMAP and PMAP standards.
