Both companies have also announced that they have reached a number of key milestones for cloud-enabled IC design, as well as for TSMC 3DFabric, TSMC’s comprehensive family of 3D silicon stacking and advanced packaging technologies.
The Siemens EDA offerings were recently certified for TSMC’s N3 and N4 processes and include the Calibre nmPlatform, Siemens’ physical verification solution for IC sign-off, as well as the Analog FastSPICE Platform, which provides circuit verification for nanometer analogue, radio frequency (RF), mixed-signal, memory, and custom digital circuits.
Siemens and TSMC have also been working closely on advanced process certifications for Siemens’ Aprisa place-and-route solution, to help assist joint customers achieve a smooth and more rapid silicon success with Aprisa at the foundry’s most advanced processes.
“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, executive vice president, IC-EDA for Siemens Digital Industries Software. “Our collaboration with TSMC delivers difference-making technologies that enable our mutual customers to deliver IC innovations to market more quickly.”
Siemens support for the latest TSMC processes also extends to the TSMC 3DFabric technology. The company has successfully completed the design requirements for TSMC’s cutting-edge 3DFabric design flows.
As part of the qualification process, Siemens has enhanced its Xpedition Package Designer (xPD) tool to support Integrated Fan-Out Wafer Level Packaging (InFO) design-rule handling with automated avoidance and correction. Calibre 3DSTACK, DRC and LVS have been enabled and certified for the latest TSMC 3DFabric technologies, including InFO, CoWoS, and TSMC-SoIC.
For customers, these 3DFabric enablement milestones translate to shorter design and signoff cycles with fewer errors associated with manual interventions.
Siemens has also partnered with TSMC to build a Design for Testability (DFT) flow for TSMC’s 3D silicon stacking architecture. Siemens’ Tessent software provides a DFT solution based on hierarchical DFT, SSN (Streaming Scan Network), enhanced TAPs (test access ports) and IEEE 1687 IJTAG (internal joint test action group) network technologies, all of which are IEEE 1838 compliant.
“Siemens continues to increase its value to the TSMC OIP ecosystem by offering more features and solutions in support of our most advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “We look forward to our continued collaboration with Siemens to help our mutual customers accelerate silicon innovations with design solutions combining Siemens’ leading-edge electronic design automation (EDA) technologies with TSMC’s latest process and 3DFabric technologies.”
