The integrated circuit (IC) package assembly planning and 3D layout vs. schematic (LVS) assembly verification workflow was developed for SPIL’s fan-out family of advanced IC packaging technologies and will be deployed across its 2.5D and fan-out package family technologies.
With the growing demand for ICs that deliver more performance and lower power consumption within ever smaller footprints, IC designs increasingly feature sophisticated packaging techniques such as 2.5D and 3D configurations.
These techniques combine one or more ICs of different functionality with increased I/O and circuit density, which in turn requires the ability to create and review multiple assemblies and LVS, connectivity, geometry and component spacing scenarios.
To help customers in deploying these advanced packaging technologies, SPIL has used Siemens’ Xpedition Substrate Integrator software and Calibre 3DSTACK software for package planning and 3D package assembly verification LVS for its advanced fanout family of package technologies.
“Our challenge was to develop and deploy a proven advanced packaging assembly planning and verification workflow that included comprehensive 3D LVS,” said Dr. Yu Po Wang, vice president of CRD for Siliconware Precision Industries. “Siemens has developed a robust and proven workflow that we will use in production to validate our fan-out family of technologies.”
SPIL’s fan-out packaging family offers additional space for routing a higher number of I/O on top of the semiconductor’s area and extending the package size with a fan-out process, which cannot be achieved with conventional advanced packaging technologies.
“Siemens is pleased to collaborate with SPIL to define and deliver the workflow and technologies needed for their advanced packaging technologies,” said AJ Incorvaia, senior vice president of Electronic Board Systems at Siemens Digital Industries Software.
