As demand for smaller, more power efficient and higher performing ICs grows so next-generation devices are increasingly featuring complex 2.5D and 3D architectures that can connect dies vertically (3D IC) or side-by-side (2.5D) so that they behave as a single device. These approaches, however, can present significant challenges for IC test, since most legacy IC test approaches are based on conventional two-dimensional processes.
To address this, Siemens has introduced the Tessent Multi-die software – said to be the industry’s most comprehensive DFT automation solution for highly complex DFT tasks associated with 2.5D and 3D IC designs. The solution works with Siemens’ Tessent TestKompress Streaming Scan Network software and Tessent IJTAG software, which optimise DFT test resources for each block without concern for impacts to the rest of the design, thereby streamlining DFT planning and implementation for the 2.5D and 3D IC era.
By using Tessent Multi-die software, IC design teams will be able to rapidly generate IEEE 1838 compliant hardware featuring 2.5D and 3D IC architectures.
“IC design organisations are seeing dramatic spikes in IC test complexity due to the rapid adoption and deployment of designs featuring densely packed dies in 2.5D and 3D devices,” said Ankur Gupta, vice president and general manager of the Tessent business unit for Siemens Digital Industries Software. “With Siemens’ Tessent Multi-die solution, our customers can be ready for the designs of tomorrow, while slashing test implementation effort and simultaneously optimising manufacturing test cost.”
In addition to supporting comprehensive test for 2.5D and 3D IC designs, the Tessent Multi-die solution can generate die-to-die interconnect patterns and enable package level test using the Boundary Scan Description Language (BSDL). In addition, Tessent Multi-die supports integration of flexible parallel port (FPP) technology by leveraging the packetised data delivery capabilities of Siemens’ Tessent TestKompress Streaming Scan Network software. Introduced two years ago, Tessent TestKompress Streaming Scan Network decouples core-level DFT requirements from the chip-level test delivery resources. This enables a bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time up to 4X.
“As the limits of traditional 2D IC design approaches become increasingly clear over time, more design teams are leveraging the power, performance and form factor advantages that 2.5D and 3D IC architectures can deliver. But deploying these advanced schemes in new design starts without first establishing a DFT strategy that acknowledges the inherent challenges these architectures present can raise costs and undermine aggressive timelines,” said Laurie Balch, president and research director for Pedestal Research. “However, by evolving DFT technology to keep pace with the rapid adoption of multi-dimensional designs, EDA vendors can play a key role in further enabling global, mainstream adoption of 2.5D and 3D architectures.”
