Spansion introduces high data rate memory interface
1 min read
Flash memory pioneer Spansion has unveiled a memory interface that improves read performance while reducing the number of pins required, as well as a family of NOR flash products which implement the interface.
The 12pin Spansion HyperBus interface consists of an 8bit address/data bus, a differential clock (two signals), one Chip Select and a Read Data Strobe for the controller. Along with supporting data transfer rates of up to 333Mbyte/s, the interface is also said to reduce overall system cost.
Spansion's HyperFlash Memory family will be available in 1.88 and 3V and 1.8V variants, with densities of 128, 256 and 512Mbit being introduced. According to Michael Skorzec, chipset and ecosystem manager with Spansion's memory group, the 512Mbit device will be the first to sample, probably in the second quarter of 2014.
HyperFlash memories, available in an 8 x 6mm BGA, will also provide an upgrade path from single Quad SPI to Dual Quad SPI to HyperFlash Memory, allowing designers to use a platform based approach to product design.
According to Skorcez, HyperBus will find wide application in high performance applications, including dashboard clusters. "These clusters are featuring larger TFT displays and these need images to be displayed more quickly. HyperBus means data doesn't need to be compressed so much." Other potential applications include hand held displays, digital cameras and home automation.
Meanwhile, Spansion says the HyperBus Interface is being implemented by leading SoC manufacturers.
