ST tapes out first 20nm test chip

The tape out represents a milestone in the R&D collaboration between the two companies to develop a comprehensive design enablement solution for SoC ICs using ST's next generation 20nm process technology. This was developed alongside its International Semiconductor Development Alliance (ISDA) partners in New York. According to Philippe Magarshack, pictured, group vice president at STMicroelectronics Technology Research and Development (R&D), R&D teams from both companies worked together over the last year to build the foundations of the 20nm design environment. "As a joint development partner of the ISDA alliance, STMicroelectronics is at the forefront of advanced process technology development," he said. "From the onset, we have worked closely with Synopsys to enable the readiness of key components in our 20nm design flow. Synopsys' technology leadership and our close R&D interaction enabled us to validate and optimise the implementation solution. The successful tapeout of our first technology demonstrator chip marks a key milestone towards 20nm readiness. Silicon is expected in Q2 2011." As part of the collaboration, Synopsys plans to strengthen its R&D presence in France.