Already demonstrated in more mature nodes, the 16nm FinFET variant of sureCore’s PowerMiser IP incorporates its power saving technologies.
According to Paul Wells, CEO at sureCore, the team at KU Leuven was able to achieve significant improvements by using the company’s PowerMiser SRAM IP, which is a low-power IP that has been developed for leading-edge devices demanding high computational loads when active as well as minimal operating and stand-by power consumption.
sureCore claims that it can reduce dynamic power by up to 50% and static/leakage power by up to 20% compared to foundry and other SRAM solutions, with savings across the full process, voltage and temperature range.
“People forget that the initial drivers for the 16nm node were mobile and HPC solutions, and hence most of the IP developed for this node was optimised for performance not power,” said Wells. “Today 16nm could almost be considered to be a mature node with many millions of devices in the field. Forward-thinking application developers are now looking to exploit this node’s improved density, leakage and power characteristics, especially for wearables, medical and Edge-AI devices. This is where our PowerMiser SRAM can bring huge benefits by enabling challenging power budgets to be delivered.”
Professor Wim Dehaene at KU Leuven (Katholieke Universiteit Leuven) commenting, said, “We licensed sureCore’s PowerMiser IP because we wanted to create a novel neural processing accelerator chip for AI applications. The chip has very high computational processing needs, and, of course, such devices naturally also have significant power consumption characteristics. We were very impressed that the sureCore solution could go so far in terms of power savings.”
PowerMiser is available in 28nm, 22nm and 16nm process nodes, and later this year sureCore plan to release a 7nm variant.
