Synopsys donates verification methodology
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Synopsys is donating its complete implementation of the VMM verification methodology for SystemVerilog, including the VMM Standard Library and VMM Applications, to Accellera, the design standards organisation.
Accellera’s recently formed Accellera Verification IP Technical Subcommittee will use the donation for its standardisation activities.
Manoj Gandhi, senior vice president and general manager of the Verification Group at Synopsys. “Accellera’s acceptance of Synopsys’ donation enables Accellera to leverage this investment to create a single, unified standard that will accelerate the pace of innovation.”
The VMM methodology, originally defined in the Verification Methodology Manual for SystemVerilog, has been used by hundreds of verification teams since its introduction in 2005. Synopsys says its donation addresses customers’ demand for a modular, scalable and reusable design methodology standard while enabling them to more easily develop and share complex verification environments.
“Accellera’s latest standardisation activity will promote interoperability among vendors’ and users’ verification methodologies,” said Shrenik Mehta, Accellera chair. “The donation of Synopsys’ VMM implementation provides the technical subcommittee with established technology to meet their objectives.”
