The addition of CXL 3 and the CXL Switch strengthens the verification of PCIe and CXL Subsystem holistically.
Commenting Nitin Kishore, CEO, Truechip, said, "CXL specification (along with NVMe) and CXL Switch helps to make the processor, memory and storage devices work more independently and reduces the churn of data between the device and the host making way for far more efficient composable heterogenous computing servers.
“CXL 3 brings additional loads of improvements like doubling the bandwidth of CXL 2 without additional latency, adding multilevel switching and fine-grained resource sharing, which will change the performance of the next generation of servers and data centres."
"In this era of increasingly complex designs, changing customer expectations and high customisation needs, Truechip aims to offer positive engagement, purpose-driven solutions and creating compelling value for its customers across the entire design cycle value chain," Kishore added.
CXL 3.0 distinguished Features:
CXL 3.0 adds 6 CXL.mem channels with inclusion of M2S Back-Invalidate Response (BIRsp) and S2M Back-Invalidate Snoop (BISnp). It also added a new flit of 256B with features including a Standard Flit and a Latency Optimisation (LO) Flit built upon PCIe flit modes.
CXL 3.0 also removed Retry Control Flit and LLCRD Control Flit and added in band error Control Flit for 256B Flit type. Also, the Retry mechanism for 256B flits will now be performed in the PHY Layer instead of Link Layer.
CXL Switch distinguished Features:
CXL switch comes with different configurations as Single VCS, Multiple VCS and with MLD Ports.
CXL Switch also supports different initialisation methods like Static and with Fabric manager based initialisations.
CXL Switch supports Hot Plug Add and Hot Plug Remove of a device.
