This IP natively integrates with SignatureIP’s recently announced iNoCulator tool to provide a high-speed interface for chip design to connect with peripherals. It has been designed from the ground up so that there is no legacy code overhead ensuring a very small footprint as well as an outstanding operating frequency of 1 GHz for Gen 6 data rate.
In addition, its already low power consumption can be further reduced by clock gating and power gating in the power management unit.
Commenting Kishore Mishra, SignatureIP’s CTO, said, “As we have designed this from scratch, we have made it modular so that features can be added or deleted to exactly meet the customer’s requirements and the configuration registers are implemented as a part of the IP. It has a layered architecture with PHY layer, Data link layer and Transaction layer. Trace and debug features are built in for rapid implementation so that the customer has a fast time to market.”
The PCIe Controller is provided as synthesisable RTL along with sample testbench and tests for easy implementation along with scripts for simulation, syntheses and timing.
As with all SignatureIP products, full documentation is provided for easy integration into a customer’s design.
