Upgrade allows SoC designers to optimise for speed, area and power
1 min read
Synopsys has extended its DesignWare portfolio with the addition of the DesignWare HPC (High Performance Core) Design Kit. Featuring a suite of high speed and high density memory instances and standard cell libraries, the kit allows SoC designers to optimise their on chip cpu, gpu and dsp IP cores for maximum speed, smallest area or lowest power – or to achieve an optimum balance of the three.
An early user of the technology was Imagination Technologies. Mark Dunn, executive vice president of IMGworks SoC Design with Imagination, said: "Our most recent project was building a PowerVR Series6 gpu core using cells and memories from Synopsys' HPC Design Kit. We achieved an overall reduction of 25% in dynamic power as well as a 10% saving on area, with some blocks achieving a 14% area improvement. We also created a tuned design flow that has delivered a 30% improvement in implementation turnaround time."
The HPC Design Kit contains fast cache memory instances and performance tuned flip-flops that enable speed improvement of up to 10% over the company's standard Duet package. To minimise dynamic and leakage power as well as die area, the kit provides area optimised and multibit flip-flops and an ultra high density two port sram, delivering reductions in area and power of up to 25% while maintaining processor performance.
John Koeter, Synopsys' vice president of marketing for IP and systems, noted: "In one package, designers now have access to the specialty cells and memories they need to optimise their cpu, gpu and dsp cores across the full speed, power and area spectrum."
