According to Transparency Market Research, the Chiplet market is expected to be valued at more than $47bn by 2031, representing one of the fastest growing segments of the semiconductor industry at more than 40% CAGR from 2021 to 2031. This growth is expected to be enabled by the considerable cost reduction and improved yields chiplets will enable as compared to traditional system-on-chip (SoC) designs.
While Chiplets can provide much greater system design flexibility, they have been limited to High Performance Computing environments using the most advanced technology nodes with per unit device costs in the tens to hundreds of dollars.
With UniPHY, however, YorChip is looking to enable lower cost solutions with the flexibility of packaged Chiplets. Currently, the lead-time and NRE cost to develop the custom substrate, chiplet package and system level test can easily exceed $500,000 and take more than six months. YorChip’s solution accelerates the design cycle to a few weeks and reduces costs by more than 80%.
“We are excited to announce the first dual-use Chiplet PHY,” says Kash Johal, CEO of YorChip. “Our mission is enabling Chiplets for mass markets, and this patent-pending technology will be key to unlocking pervasive use of Chiplets in mass markets for all customers, small, medium and large.”
“The key invention here is simultaneously supporting the spectrum of ESD standards for Chiplets in die form (50V) and traditional packages (250V),” explained Ahmad Tavakoli, VP Analog of YorChip, “while maintaining ultra-low power of chiplets over traditional I/O such as LVDS/GPIO. Packaged Chiplets are suitable for customers seeking fast time to market, more robust markets and low cost solutions.”
